The high costs associated with microcircuit manufacture are strong encouragement for determining the acceptability of microdevices at the earliest possible stage of manufacture. Therefore, functional testing at the semiconductor wafer level is preferred over testing at: (a) the microcircuit die (a bare, non-incapulated chip) level, or (b) the finished microdevice level. Conventional chip testing methods to determine the reliability of semiconductor chips have primarily relied upon one of the two industry standard procedures: (a) wafer probing, or (b) statistical sampling. Only the first method, wafer probing, applies at the wafer level; statistical sampling is done at the microcircuit die level of production.
At the wafer level, probing technology is generally accomplished at room temperature by introducing electrical signals to the necessary circuits of individual devices to check for appropriate circuit performance. A semiconductor wafer is approximately eight inches in diameter and may contain an array of from 50 to 5000 microdevices of the same type.
As wafer probing is typically done at room temperature, performance of the microdevice is not evaluated under the thermal load equivalent to full circuit operation in the microdevice=s final form. Thermal screening at the wafer level is not technically feasible since a thermal forcing technique is not yet available that can rapidly cycle the relatively large mass of a four or five inch semiconductor wafer. Therefore, chip integrity is still questionable after wafer probing.
Next, the devices are cut from the wafer along a preplanned grid, called "streets", and separated into individual microcircuit die. Damage incurred during the wafer cutting process is normally evaluated only by visual inspection. The die may be tested at this stage of production to determine the individual reliability of the microchip before incorporation into a larger assembly, sometimes known as a Hybrid Microelectronic Assembly (HMA). However, exhaustive testing of individual die is not economically practical; therefore statistical sampling of the die batch may be employed.
Statistical sampling is the other industry standard microchip testing procedure used to determine electrical function and operating reliability. Using this methodology, one to two percent of the individual die are separated from the wafer, mounted into a custom test fixture, and subjected to dynamic electrical and thermal evaluation. Based upon the compiled test results, predictions are then made concerning the other 98 to 99 percent of chips from that batch. Chips, which were used for testing, are generally not commercially useable after having been mounted in the fixture and tested.
At the next stage of production electrical wires are attached to the bond pads to provide connectivity between the integrated circuits on the die and the final electrical circuit. The attachment of wires to the bond pads traditionally introduces certain stresses into the microcircuit, primarily in the area beneath the bond pads. The die are subsequently encapsulated into their final electrical package, an HMA. At this level, the final product can again be tested for proper functionality; however, the entire cost of production has already been expended and a failure at this level may result in a total waste of the microchip.
Therefore, for the most part, chip reliability is uncertain until the chips are assembled in the final electrical package, and the completed HMA package is subjected to final testing. At this point in the manufacturing process, non-functional HMA packages must undergo labor intensive troubleshooting to determine the cause and extent of failure. In many cases the cost of repairing a faulty HMA package exceeds the cost of producing the entire package.
One method of on-wafer functional testing currently in use is that of built-in test (BIT) or built-in self test (BIST). During these tests, a portion of the semiconductor wafer is designed and manufactured to create the signals that test specific critical modules of the individual devices, when appropriately driven by external test equipment. Unfortunately, however, the BIST circuitry is conventionally placed within the principal area of the microchip. The presence of the BIST circuitry takes away valuable space that could otherwise be used for additional primary circuitry. Therefore, the capability of testing the circuit comes at the high price of sacrificing space within the microchip area, and the useable chip density of the wafer is reduced by the area dedicated to BIST.
Accordingly what is needed in the art is a device and methodology that provides a BIST circuit without reducing the area dedicated to the primary circuitry.